A memory controller device. The memory controller includes a first circuit to capture a first bit of data in response to a rising edge of a strobe signal and a second circuit to capture a second bit of data in response to a falling edge of the strobe signal. The memory controller device also includes a first register circuit coupled with the first circuit where, in operation, the first register circuit samples the first bit of data from the first circuit in response to a clock signal and is adjustable to select which transition of the clock signal is employed to sample the first bit of data. The memory controller device additionally includes a second register circuit coupled with the second circuit. The second register circuit, in operation, samples the second bit of data from the second circuit in response to the clock signal and is adjustable to select which transition of the clock signal is employed to sample the second bit of data.