An arithmetic circuit is provided having a compact and high-speed logic-in-memory wherein various operations are performed. The arithmetic circuit includes a memory element having a variable resistance element R in which the state of resistance changes reversibly between the state of high resistance and the state of low resistance by applying voltages with different polarities between one electrode and the other electrode, and at least one transistor of MRD, MRS, MW1 and MW2 connected respectively to both ends of the memory element; wherein data is stored in the memory element, the operation for the external data X, W, Y1 and Y2 input through any of the transistors is performed by applying potential to each of the ends of the memory element through the transistors MRD, MRS, MW1, and MW2, and a result of the operation is output from the memory element.