A thin film transistor array panel is provided, which includes: a substrate; a plurality of first signal lines formed on the substrate; a plurality of second signal lines intersecting, and insulated from, the first signal lines; a plurality of pixel electrodes formed in intersection areas of the first and second signal lines; a plurality of first thin film transistors electrically connected to the first signal lines, the second signal lines, and the pixel electrodes; a plurality of buffer electrodes capacitively coupled to the pixel electrodes and located at a boundary of the intersection areas; and a plurality of second thin film transistors electrically connected to the buffer electrodes and the first signal lines, wherein the first signal lines are connected to the pixel electrodes of a previous row.