Single-crystalline silicon layers 7a and 7b are selectively formed on LDD layers 5a and 5b by an epitaxial growth method. Opening sections 10a and 10b are formed, which expose a source layer 8 and a drain layer 8b, respectively, through an interlayer dielectric film 9 and the single-crystalline silicon layers 7a and 7b, respectively, and then, plugs 12a and 12b are formed in the opening sections 10a and 10b embedded through barrier metal films 11a and 11b, respectively.