A central processor unit (CPU) accesses memory to read and write data and to read and execute program instructions. A problem arises when accessing slower Flash or electrically programmable read only memory (EPROM) with a faster CPU. A method and system has been devised which uses interleaving techniques and memory sub-sections. A memory interlace controller interfaces a faster CPU to several sub-sections of slower memory. The memory interlace controller interlaces the access of the slower memory and thus optimizing the CPU system speed.