Methods are provided for forming a circuit component on a workpiece substrate. The methods comprise the steps of depositing a dielectric material over the substrate; etching a pattern through the dielectric material to expose a portion of the substrate; depositing a barrier metal over the dielectric material and the exposed portion of the substrate; depositing a conductive metal over the barrier metal, the deposited conductive metal having a thickness sufficient to fill the etched pattern; planarizing the conductive metal to form a planar metal layer; and polishing the metal layer and the barrier metal in a single polishing step using an abrasive-free polish until the dielectric material surrounding the pattern is exposed.