A programmable frequency divider capable of operating in a normal mode and a fractional mode divides the input clock frequency by any integer `N` provided at the input. In the normal mode the input is divided by the integer `N`. The divided output signal has a 50% duty cycle if the input clock has a 50% duty cycle. In the fractional mode, fractional division can be achieved from dividing by 1.5 to dividing by 255.5 in steps of 0.5.