A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction. The instruction is specified by the Pentium III PREFETCH opcode preceded by the REP string instruction prefix. The programmer specifies the count of cache lines to be prefetched in the ECX register, similarly to the repeat count of a REP string instruction. The effective address of the first cache line is specified similar to the conventional PREFETCH instruction. The REP PREFETCH instruction stops if the address of the current prefetch cache line misses in the TLB, or if the current processor level changes. Additionally, a line is prefetched only if the number of free response buffers is above a programmable threshold. The prefetches are performed at a lower priority than other activities needing access to the cache or TLB.