A method, apparatus and program product for testing at least one scan chain in an electronic chip in which the scan chain is formed by shift register latches arranged in the chain having a scan path with input pins and output pins. A flush test is executed for the scan chain under test and the flush test diagnostics for the flush test are recorded. A scan test is then executed for the scan chain under test and further test diagnostics are recorded in the event either or both the flush test or the scan test fails. The recorded flush test diagnostics and further test diagnostics are then analyzed to identify a call to one or more probable failed or failing shift register latches in the tested scan chain. The further scan chain diagnostics may include Disturb, Deterministic, ABIST, LBIST and Look-Ahead diagnostics. The tests may also be conducted for different voltage levels to determine the sensitivity of the scan chain being tested to differing voltage levels.