Identification of a faulty net in a design implemented on a programmable logic device (PLD). In one approach, configuration data is generated to implement a duplicate circuit of a failing sub-circuit in the design. The PLD is configured with the configuration data that implements the failing sub-circuit and the duplicate circuit, and at least one set of input signals is applied to the sub-circuit and the duplicate circuit. A signal from each net in the sub-circuit is compared on the PLD to a corresponding net in the duplicate circuit. In response to the signal from the net in the sub-circuit being unequal to a signal from the corresponding net in the duplicate circuit, the net in the sub-circuit is identified as faulty.