A data processing system (10) has a system debug module (19) coupled to a processor (12) for performing system debug functions. Located within the system, and preferably within the processor, is debug circuitry (32) that selectively provides debug information related to the processor. The circuitry identifies which of a plurality of registers (26) is sourcing the debug information. A user-determinable enable and disable mechanism that is correlated to some or all of the registers sourcing the debug information specifies whether to enable or disable the providing of the debug information. In one form a single bit functions as the mechanism for each correlated register. Debug operations including breakpoints, tracing, watchpoints, halting, event counting and others are qualified to enhance system debug. The registers may be included in a programmer's model and can be compliant with one or more industry debug related standards.