A memory device includes a memory cell having a read margin that exceeds the MR ratio of the memory cell's MR element. The memory cell includes a MR element, a reference transistor, and an amplifying transistor. In some embodiments, the MR element can include a magnetic tunneling junction sandwiched between electrode layers. One of the electrode layers can be connected to an input node, which is also connected to the drain or source node of the reference transistor and the gate node of the amplifying transistor. The drain node of the amplifying transistor is connected to a sense amplifier via a conductive program line. The memory cell uses the current through the MR element to control the gate-source voltage of the amplifying transistor, and senses the state of the memory cell based on the voltage drop (or current loss) across the amplifying transistor.