A multiple-core processor providing a flexible cache directory scheme. In one embodiment, a processor may include a second-level cache including a number of cache banks and a respective number of cache directories corresponding to the cache banks. The processor may further include a number of processor cores configured to access the cache banks, as well as core/bank mapping logic coupled to the second-level cache and the processor cores. Each of the processor cores may include a respective first-level cache. Each of the respective cache directories may be configured to store directory state information associated with portions of respective first-level caches of at least two of the processor cores. If fewer than all of the cache banks are enabled, the core/bank mapping logic may be configured to completely map directory state information associated with each respective first-level cache of enabled processor cores to respective cache directories associated with enabled cache banks.