A method of transforming a first topology to a reduced topology is disclosed. One preferred embodiment of the present invention includes a method of transforming a circuit from a first topology to a reduced topology, said first topology comprising a plurality of inter-connected circuit elements. The method comprises the steps of: (a) identifying one or more circuit elements; (b) analyzing the effect of reducing one or more of said identified circuit elements on the topological and physical characteristics of said circuit; and (c) if the effect satisfies a first standard, generating a second topology reflecting the reduction of one or more identified circuit elements.

 
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> Parameter checking method for on-chip ESD protection circuit physical design layout verification

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