A memory data protection system is disclosed, which comprises a memory circuit, a protection contents indicating section which stores a security bit and a protection bit, a protection function circuit which determines permission/prohibition of reading of data from the memory circuit and permission/prohibition of writing of data to the memory circuit in accordance with the security bit and the protection bit, and a protection function locking/unlocking circuit which makes the protection function circuit in a lock state to forcibly prohibit reading of data from the memory circuit and writing of data into the memory circuit in a time period from when a power supply is turned on till when the protection function circuit completes reading of the security bit and the protection bit from the protection contents indicating section into data buses, and after lapse of the time period, the protection function locking/unlocking circuit unlocks the lock state.

 
Web www.patentalert.com

> Establishing command order in an out of order DMA command queue

~ 00361