Testing methods and chips preventing sampling errors caused by asynchronous effect. The chip comprises a first logic portion driven by a first clock signal with a first operating frequency, and a second logic portion driven by a second clock signal with a second operating frequency. The first operating frequency is higher than the second operating frequency, and is not an integral multiple of the second operating frequency. In the test method, a third operating frequency of a third clock signal is generated according to the second clock signal, in which the third operating frequency is higher than the first operating frequency and is an integral multiple of the second operating frequency. The first clock signal is replaced by the third clock signal and the first logic portion is tested by the third clock signal. The second logic portion is tested by the second clock signal.