In one embodiment of the invention, a method for unified debug for simulation, includes: generating a transaction from a hardware verification language (HVL) testbench; copying signal states in the HVL testbench after the transaction is generated, wherein the signal states are copied in a hardware description language (HDL) mirror; generating a response to the transaction from a device-under-test (DUT); and displaying the signal states in the HVL testbench on a display screen as a first waveform, and displaying the DUT response on the display screen as a second waveform. In another embodiment of the invention, an apparatus is provided for unified debug for simulation, where the apparatus can perform the above method.