The present invention discloses a square root algorithm that uses a multiplication operation, an exclusive-or operation, a bit right shift operation, a bit left shift operation and a comparison operation to compute a square root for an integer in a binary form, such that more computations can be processed in a shorter time, and lower the cost for a programmable digital calculator and digital circuits which comes with a central processing unit of a computer system, and thus allowing the algorithm of the present invention to be used extensively.

 
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> Multiplier device

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