An upper-level host has a control unit and a host controller for controlling the operation of a device. The host controller includes a buffer memory that reads data from the device into the buffer memory. The control unit reads data from the buffer memory and handles interruptions from the device. Moreover, the host controller reads data for every unit amount from the device with a part of the data of predetermined capacity left in the device, and reads data corresponding to a part of the data of predetermined capacity from the device into the buffer memory if the buffer memory is empty as the data in the buffer memory is transferred to the control unit.