Image processing device is able to obtain digest video of an actual video with a simple configuration and has processor that generates simulation video data, image display control circuit that converts simulation video data into video signal and displays video signal on a display device, primary buffer that reads the simulation data and stores data of simulation data for a continuous predetermined period of time, wherein the processor detects occurrence of predetermined conditions in simulation data, and a digest replay buffer stores, as one scene of digest data, and data is stored in the primary buffer prior to the time of the occurrence of the predetermined conditions and simulation data for a period of time from when predetermined conditions occurred until when the storage termination conditions are satisfied.