A semiconductor memory device includes a memory cell array which has a plurality of memory cells, a plurality of first bit line pairs which transfer data among the memory cells, a plurality of second bit line pairs disposed corresponding to the plurality of first bit line pairs, a plurality of variable resistance elements disposed to connect the plurality of first bit line pairs to the plurality of second bit line pairs, a plurality of data line pairs disposed corresponding to the plurality of second bit line pairs, a plurality of input/output gates which transfer data between the plurality of second bit line pairs and the plurality of data line pairs, a plurality of sense amplifier circuits which amplify data transferred to the plurality of second bit line pairs, and a bit line isolation control circuit which controls resistance values of the plurality of variable resistance elements.