A low drop-out voltage regulator having a pass device (Mp), an error amplifier (M1-M51) and a double regulation loop including DC feedback loop (R1, R2) and an AC feedback loop (Rf, Cf) including a high pass filter (Cf). Combining these two loops creates an ultra low frequency internal pole which makes the regulator stable substantially independent of the output bypass capacitor's value. This provides the following advantages: allows the use of very low bypass capacitors; allows to extend the PSRR frequency behavior; allows an increase in the regulator's efficiency (reduced power consumption on heavy loads).