A method for optimizing low threshold-voltage (V.sub.t) devices in an integrated circuit design. The method includes identifying paths and nodes within the integrated circuit design, determining node overlap within the integrated circuit design, calculating possible solutions for addressing timing violations within the integrated circuit design, choosing a solution for addressing timing violations, inserting low V.sub.t devices at particular nodes of the integrated circuit design, and repeating the calculated possible solutions wherein choosing a solution and inserting low V.sub.t devices at particular nodes to address timing violations within the integrated circuit design.