An apparatus and method for controlling and providing a robust, single
entry cache memory is described in connection with an on-board cache
memory integrated with a microprocessor. By implementing the single entry
cache memory in a redundancy array of the cache memory, CPU debug
procedures may proceed independently of the cache debug by disabling part
of the cache memory and enabling a dedicated single entry cache in the
redundancy array. Use of a cache redundancy array for the single entry
cache imposes no area or latency penalties because the existing cache
redundancy array already matches the latency of the cache.