A split-gate flash memory device has a floating gate with a lateral recess at its bottom sidewall by adding an undercutting step. The split-gate flash memory device has a floating gate with a lateral recess on a substrate, an integrated dielectric layer lining the substrate, the sidewall and the lateral recess of the floating gate; a control gate on the integrated dielectric layer and covering at least part of the floating gate; and a dielectric spacer in the lateral recess between the integrated dielectric layer and the control gate.