A parallel lookup memory (PLM) is provided. The PLM includes a content addressable memory (CAM) array having a plurality of CAM entries. Each CAM entry has at least two storage location, and one of the locations includes value matching logic. The PLM also includes a PLM controller, which, responsive to an external command, applies a search value to a sub-set of the CAM entries. The sub-set and search values are identified by the external command, which includes data identifying CAM entries that are a start and end location of the sub-set, or data identifying a CAM entries that is a start of the sub-set and a length identifier representing a number of CAM entries to be searched. The PLM may be provided in a processor core, in a processor chip external to a processor core as a counterpart to a layer of cache, or in a multiprocessor computer system having a number of agents coupled to an external communication bus, where the PLM is provided in a first agent and a processor is provided in a second agent.