A data transfer control device including: a link controller which analyzes a received packet transferred from a host-side data transfer control device through a serial bus; an interface circuit which generates interface signals and outputs the generated interface signals to an interface bus; and an internal register in which is set interface information for specifying signal types of the interface signals output from the interface circuit. The interface circuit includes first to Nth interface circuits (N is an integer greater than one), and each of the first to Nth interface circuits generates an interface signal of a signal type according to the interface information set in the internal register.