A system and method for manufacturing micro cavities at the wafer level using a unique, innovative MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed, with epoxy bonded single-crystalline silicon membrane as cap and deposited and/or electroplated metal as sidewall, on substrate wafers. The epoxy is also the sacrificial layer. It is totally removed from within the cavity through small etch access holes etched in the silicon cap before the etch access holes are sealed under vacuum. The micro cavities manufactured therein can be used as pressure sensors or for packaging MEMS devices under vacuum or inert environment. In addition, the silicon membrane manufactured therein can be used to manufacture RF switches.

 
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> Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties

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