A test circuitry approach which addresses the shortcoming associated with current process monitor circuitry. The approach provides a means of testing that can be employed in association with any and all tester platforms. On-chip built-in self test (BIST) circuitry is added to the design that analyzes the 10-bit value captured from the counter, and indicates to the ATE via a single pin at a single test vector location whether or not the device has passed its test limits. An alternative solution is to use the digital capture circuitry on a mixed-signal tester to capture the non-deterministic digital word generated by the process monitor circuitry, and then test that result against the desired test limits.