A method for producing a chip is disclosed. A first step of the method may
involve first fabricating the chip only up to and including a first metal
layer such that a core region of the chip has an array of cells, each of
the cells having a plurality of transistors. A second step of the method
may be to design a plurality of upper metal layers above the first metal
layer in response to a custom design created after the first fabricating
has started, the upper metal layers interconnecting a plurality of the
cells to form an electrostatic discharge clamp at a power domain
crossing. A third step may include second fabricating the chip to add the
upper metal layers.