A chip carrier for flip chip applications, according to the present invention, provides peripheral bumps and inner bumps. The inputs and outputs related to the inner bumps are routed out on an additional wiring layer by means of vias. The proposed bond layout provides a high I/O count for a predefined chip size and a predefined carrier technology.

 
Web www.patentalert.com

> Bump electrodes having multiple under ball metallurgy (UBM) layers

~ 00377