A test arrangement with a test memory chip and a control device is
provided. Error correction data are stored in the test memory chip with
the aid of the control device. In the case of an error event, it is
ascertained whether the error occurred on the error correction chip. If
so, the memory controller compares the data stored in the error
correction chip with the data of the auxiliary memory. The address of the
error correction chip can be deduced from the address of the auxiliary
memory, thereby enabling unambiguous addressing of a defective memory
cell of the error correction chip.