A memory circuit with an error correcting system comprising an address bus
(102), an input data bus (108), and an output data bus (115), the circuit
comprising a memory having an address bus (113), a data bus (114) and an
error correcting circuit comprising an encoder (107). A first address
register (104) is connected to the input address bus of the circuit for
successively storing addresses corresponding to memory write operations
only. A second data register (105) is connected to the input data bus of
the circuit (108) for storing data transmitted to the encoder (107).
Circuits make it possible to introduce a one-cycle shift into the memory
writes, without modifying reads, giving the encoder more time to compute
error correcting codes.