A frame signal phase adjuster comprises units for inputting a parallel clock and a reference signal (22-4 and 22-1); generating a frame signal from the reference signal (22-1), adjusting a phase of the frame signal (22-3), generating an adjusted frame signal synchronized by the parallel clock from the parallel clock and the adjusted frame signal (22-4), generating a frame reset pulse signal based on the parallel clock and the adjusted frame signal synchronized by the parallel clock (22-2), and outputting the frame reset pulse signal (22-2). The unit (22-4) adjusts the phase of the frame signal so that the frame signal is constantly HIGH or LOW throughout a setup time and a hold time.