A dual port memory is updated at substantially the same data sampling rate as a clock frequency of the dual port memory. The dual port memory stores data relating to each different parameter value in a stream of data samples, and provides the stored data from an address in the memory corresponding to the received parameter value. An updating element updates stored data and provides the updated data to an input of the dual port memory for writing back into the address corresponding to the received parameter value. A first port of the dual port memory is utilised as the output of the dual port memory coupled to the input of the updating element on a first clock cycle of the dual port memory, and a second port of the dual port memory is normally utilised as the input of the dual port memory coupled to the output of the updating element on a second clock cycle, the next address being accessed via the first port on the second clock cycle. A comparator receives the parameter value on the first clock cycle of the dual port memory and a next received parameter value on a second clock cycle, and provides a match signal if the received parameter value and the next received parameter value are the same. The match signal is utilised to enable the first port of the dual port memory to be used as the input for the second clock cycle so that the data updated by the updating element on the first clock cycle is provided at the first port rather than the second port and is therefore correctly provided to the input of the updating element on the second clock cycle.