Transmission convergence sublayer circuit is coupled between a buffer and a deframer. The deframer submits a data stream enable signal and data bytes to the circuit. The data stream enable signal enables the circuit so that multiple groups of byte data belonging to a data cell are received and temporarily stored inside a byte-wise data pipeline. A header cyclic redundancy checker also receives the byte data and then conducts a header search. An idle cell identifier is used to determine if the data cell is a non-idle cell. When the header is found and determined to be a non-idle cell, a descrambler retrieves payload data of data cell from the byte-wise data pipeline and conducts a descrambling operation after obtaining a quantity of data equal to a double word. Ultimately, the double word data is output to the buffer with minimum delay.