The most hardware efficient way to implement an N-stage pipeline ADC is to use (G+1)-level ADC-DAC for its first (N-1) stages and use (2G-1)-level ADC for the last stage, where G is the inter-stage gain. For the fist (N-1) stages using (G+1)-level ADC-DAC, the (G+1) levels are uniformly distributed between -(G-1)/G and (G-1)/G; inclusively. The spacing between two adjacent levels is 2(G-1)/G.sup.2. For the last stage using (2G-1)-level ADC, the (2G-1)-levels are uniformly distributed between -(G-1)/G and (G-1)/G, inclusively. The spacing between two adjacent levels is 1/G.