A shadow RAM or "non-volatile SRAM" memory cell is implemented in a much smaller area by building the cell upward rather than outward. By stacking non-volatile storage devices above or below an SRAM cell, a smaller cell can be provided and result in a lower cost memory device. In certain embodiments, such a memory cell includes a pair of cross-coupled devices disposed on a first device layer and defining a pair of internal cross-coupled nodes, and a pair of non-volatile storage devices disposed on a second device layer above or below the pair of cross-coupled devices and coupled to the cross-coupled nodes.