A short detect and safeguard mechanism is incorporated into a processor and/or a motherboard. A processor includes a first power path to receive a VCC voltage and a second power path to receive a VSS voltage. A processor core executes instructions and is coupled to the first and second power paths to receive the VCC and VSS voltages. A short detect circuit is coupled to detect a short between the first and second power paths. If the short detect circuit detects a short, then it generates a short signal. The short signal is received by a voltage identification ("VID") module provided to select the VCC voltage. In response to the short signal, the VID module generates a disable VCC code.