A VLIW processor comprising a plurality of functional units (1, 3, 5, 7),
a distributed register file (9, 11, 13, 15) accessible by the functional
units (1, 3, 5, 7), a partially connected communication network (17) for
coupling the functional units (1, 3, 5, 7) and selected parts of the
distributed register file (9, 11, 13, 15), characterized in that the VLIW
processor further comprise a communication device (29) for coupling the
functional units (1, 3, 5, 7) and the distributed register file (9, 11,
13, 15).