Processing circuitry for a pagewidth printhead includes a bus. A processor is connected to the bus to control operation of the processing circuitry. Page data input circuitry is connected to the bus to permit compressed page data to be communicated to the processing circuitry. Expansion circuitry is connected to the bus to expand the compressed page data. Halftoning and compositing circuitry is connected to the bus to halftone and composit expanded page data. Printhead interface circuitry is connected to the bus to permit page data to be communicated to the pagewidth printhead. Quality assurance interface circuitry is connected to the bus to permit communication between the processing circuitry and a quality assurance integrated circuit device mounted on an ink cartridge that supplies ink to the printhead.