Method and apparatus for evaluating different digital data channel configurations. A digital data channel stores input data to a recordable medium and retrieves readback data from the medium. The input data are arranged into an input sequence of symbols of selected symbol length, and the readback data are arranged into an output sequence of symbols of the selected symbol length. Comparing the output sequence to the input sequence allows identification of the number of erroneous symbols for the selected symbol length. Different input and output sequences are generated using different symbol lengths from the same input and output data. In this way, error rate performance can be predicted for different error correction code (ECC) and run length limited (RLL) encoding scheme combinations. The steps are carried out by an emulation system preferably comprising a field programmable gate array (FPGA) which inhibits and emulates selected portions of the digital data channel.