A multiplexed FIR/IIR digital filter structure (300) which offers linear
phase response and low group delay by switching on a FIR filter portion
(31) or a IIR filter portion (32). To reduce the silicon area, the
FIR/IIR filter (300) shares registers which is enabled because the FIR
and IIR processing do not use the registers at the same time but rather
consecutively. Further, the multiplexed FIR/IIR digital filter structure
(300) can offer limit-cycle-free IIR operation using two's-complement
truncation in combination with positive valued allpass coefficients.