Systems and methods for implementing counters in a network processor with
cost effective memory are disclosed. Embodiments include systems and
methods for implementing counters in a network processor using less
expensive memory such as DRAM. A network processor receives packets and
implements accounting functions including counting packets in each of a
plurality of flow queues. Embodiments include a counter controller that
may increment counter values more than once during a R-M-W cycle. Each
time a counter controller receives a request to update a counter during a
R-M-W cycle that has been initiated for the counter, the counter
controller increments the counter value received from memory. The
incremented value is written to memory during the write cycle of the
R-M-W cycle. A write disable unit disables writes that would otherwise
occur during R-M-W cycles initiated for the counter during the earlier
initiated R-M-W cycle.