A semiconductor memory device for performing an OCD calibration control operation to adjust a data output impedance includes a decoder for decoding an address signal to generate an OCD default control signal, an OCD operation signal and plural data, a code generator for receiving plural-bit data to generate an OCD control code; a first circuit for receiving the OCD control code and the OCD operation signal to generate a plurality of impedance adjustment control signals; and a second circuit for receiving the plural data and adjusting the data output impedance in response to the plurality of impedance adjustment control signals.

 
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> Noisy clock test method and apparatus

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