In this clock control circuit and this clock control method, during a standby-mode of a CPU, a low-speed clock is supplied. Processings including timer processing and receiving processing are carried out by low-speed operation at the CPU. When an interrupt signal is inputted to the CPU which is in the standby mode, a high-speed clock source is activated, and counting of the low-speed clock is started at a counter. When a count value of the counter reaches a set value of a register, a high-speed clock is selected by a selection signal. The high-speed clock is supplied to the CPU, and interruption processing is started.