The invention discloses a frequency divider using half-adding functions, comprising one latch circuitry with half adding function for each digit, each latch circuitry receiving its output signal Sout at its S-input, the latch circuitry (76) for the least significant bit receiving at its Carry-input a "1", and each further latch circuity receiving at its Carry-input the carry signal from the latch circuitry of the previous digit, and an And gate circuitry receiving the Sum outputs of the latch circuitries.