An error correction circuit includes a selected-bit reverse circuit, an ECC circuit, a checkbit generation circuit, an ECC data register, a bit-comparing circuit, and an address memory unit. The selected-bit reverse circuit includes memory data and check data from the memory unit. The ECC circuit corrects a one-bit error. The checkbit generation circuit generates checkbits. The ECC data register stores the corrected data and the checkdata. The bit-comparing circuit compares each bit between the output data A from the selected-bit reverse circuit and the output data A' from the ECC data register. The address memory unit stores an address corresponding to the memory data when the bit-comparing circuit detects a discrepancy among the data A and the data A'. The error data memory unit writes the discrepancy information at the bit-location. The data OR circuit generates the first signal.