The design of a synchronous digital circuit (1) can be modified. The circuit comprises a number of clocked storage devices (2, 3, 4, 5,) and a number of combinational logic elements defining combinational paths (6, 7, 8, 9,) between at least some of said clocked storage devices. Each combinational path from an output of one clocked storage device to an input of another has a minimum delay value (D.sub.min) and a maximum delay value (D.sub.max). The actual delay of the path assumes a value between the minimum and maximum delay values. The method comprises the steps of identifying the path (6; 7; 8; 9) having the greatest difference between the maximum delay value (D.sub.max) and the minimum delay value (D.sub.MIN), and reducing said difference by increasing the minimum delay value for the path having the greatest difference. With the method a higher clock frequency for the circuit can be achieved.