A CMOS constant voltage generator circuit having input and output stages and at least one compensation stage. Each stage can comprise a single transistor or more typically a transistor stack. Current mirroring is performed between the input stage and compensation stage, as well as preferably between the input stage and output stage. The compensation stage also provides additional biasing to a transistor in the output stage to increase voltage regulation. Optionally, degeneration resistors (passive or active) are coupled to the source side, drain side, or a combination of source and drain sides in the compensation and output stages. Optionally, additional diode-coupled transistors are incorporated in the transistor stack of the output stage. The circuit provides accurate voltage reference (V.sub.ref) output with lowered sensitivity to temperature and supply voltage.